The state of electronics has advanced to a point in which various, often complex features are implemented by a particular circuit configuration. For example, the integrated circuits forming various consumer and professional devices, such as cellular telephones, smart phones, personal digital assistants (PDAs), tablet devices, computer systems, video displays, televisions, set top boxes, digital video recorders, network devices, etc., are often adapted to not only implement robust features but may implement a plurality of different features.
Various programmability may be provided in the circuit implementation to facilitate configuring of features and/or selection of particular features available using the circuitry. Such programmability may be provided in an integrated circuit configuration, such as a relatively large scale integrated circuit, to accommodate for process-voltage-temperature (PVT) variations and/or for debugging purposes. As another example, a particular integrated circuit configuration may utilize digitally programmable analog blocks (e.g., analog circuits that perform functions such as automatic gain control, band selection, filter pole re-adjustment, temperature compensation, etc.), whereby a digital block implementing the digital programmability facilitate adjustment of one or more corresponding analog blocks.
Although such programmability may be desirable in providing flexibility with respect to the functionality provided, implementing such programmability within various circuitry is not without difficulty. For example, circuit operation in each of the different states enabled by the programmability must often be tested in order for the circuitry and/or resulting device to comply with delivery requirements or other demands. As more and more programmability is introduced to the various circuits, the problem of testing the circuits grows exponentially.
Testing techniques have been developed to provide at least some level of testing with respect to the programmability of circuitry. For example, in post silicon testing commonly in use today the purely digital blocks of the circuitry are tested using a scan chain whereby every flip-flop of the digital block is programmed into a certain state, the functional mode is run for one cycle using a simple scan input test pattern, and the outputs of the scan chain observed. The scan chain testing technique is operable without actually entering the functional mode of the circuitry under test, and thus may be performed in a separate test mode. Although such a scan chain provides a relatively fast testing technique, whereby simple test patterns may be utilized to detect stuck faults with respect to digital circuitry, such a scan chain testing technique is not ideal for all circuit configurations. For example, circuitry in which a full scan design cannot be implemented (e.g., circuitry having sequential circuits, such as memory elements that are not part of the scan chain) require sequential pattern generation for testing resulting in more complex and time consuming testing. Moreover, the scan chain testing technique can only be implemented through a purely digital circuit. When the circuitry under test comprises a digital block which is deeply embedded inside an analog block, the use of a scan chain becomes problematic if not impossible.
In an attempt to address the foregoing issues with the scan chain technique, a testing technique referred to a boundary scan has been used. In the boundary scan technique, special flip-flops which only activate during the test mode are placed so as to dispose a part of the digital logic (e.g., a digital logic element of the sequential or embedded digital block) inside of those two flip-flops. In operation, the boundary scan thus measures the stuck faults using a sensor configuration disposed inside of the circuitry under test. However, the introduction of such a boundary testing configuration is only possible for non-sensitive and non-critical nodes where adding an additional flip-flop and the associated loading is not an issue with respect to the normal, non-test mode operation of the circuit under test. Moreover, a boundary test implementation is not possible with respect to all circuit configurations.
A testing technique that might be implemented, such as with respect to a circuit node sensitive to the addition of a boundary scan flip-flop configuration, is to provide circuit node as a test point directly to the tester. In such a technique, all of the sequencing and capturing of output is performed outside of the circuit under test (i.e., by the tester). Assuming that the tester is equipped with a suitably high resolution analog to digital converter (ADC), this test point scan technique may provide desired testing of the circuit under test. However, such a test point implementation is very likely to introduce ground noise. The introduction of such ground noise would require multiple samples to be captured for averaging, thereby requiring longer testing times. Moreover, since a larger out of circuit load must be charged, each sample capture would be slower.
From the above, it can be appreciated that not all circuitry is well suited for, or compatible with, implementation of existing testing techniques such as scan chain, boundary scan, or test point scan. Such circuitry may nevertheless be tested with a functional test, wherein the full operational mode of each functionality is tested (e.g., full sweep of all signals or operational situations). For example, attenuation settings can be tested by providing radio frequency (RF) input throughout the operating bandwidth of the circuit and checking output power through the full signal chain. However, such functional tests are also typically not ideal. In particular, it is generally expensive and very time consuming to perform a full functional test of circuitry, particularly if a functional mode must be implemented in order to test just for logical errors in the programmability. Moreover, some minor programmability (e.g., bias current control) may not have any significant change in output parameter and thus the programmability may not be observable at all using a functional test.